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Ultra Low Power/High Speed CMOS SRAM 512K X 16 bit
Pb-Free and Green package materials are compliant to RoHS
BH616UV8010
n FEATURES
Y Wide VCC low operation voltage : 1.65V ~ 3.6V Y Ultra low power consumption : VCC = 3.6V Operation current : 12mA (Max.)at 55ns 2mA (Max.) at 1MHz Standby current : 2.5uA (Typ.) at 3.0V/25OC VCC = 1.2V Data retention current : 1.2uA (Typ.) at 25OC Y High speed access time : -55 55ns (Max.) at VCC=1.65~3.6V -70 70ns (Max.) at VCC=1.65~3.6V Y Automatic power down when chip is deselected Y Easy expansion with CE1, CE2 and OE options Y I/O Configuration x8/x16 selectable by LB and UB pin. Y Three state outputs and TTL compatible Y Fully static operation, no clock, no refresh Y Data retention supply voltage as low as 1.0V
n DESCRIPTION
The BH616UV8010 is a high performance, ultra low power CMOS Static Random Access Memory organized as 524,288 by 16 bits and operates in a wide range of 1.65V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical operating current of 1.5mA at 1MHz at 3.6V/25OC and maximum access time of 55ns at 1.65V/85OC. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2) and active LOW output enable (OE) and three-state output drivers. The BH616UV8010 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BH616UV8010 is available in DICE form, JEDEC standard 48-pin TSOP-I and 48-ball BGA package.
n POWER CONSUMPTION
POWER DISSIPATION PRODUCT FAMILY OPERATING TEMPERATURE
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PKG TYPE
VCC=1.8V 10MHz fMax.
VCC=3.6V
VCC=1.8V
1MHz
VCC=3.6V 10MHz
fMax.
1MHz
BH616UV8010DI BH616UV8010AI BH616UV8010TI Industrial -40OC to +85OC 15uA 12uA 2mA 6mA 12mA 1.5mA 5mA 8mA
DICE BGA-48-0608 TSOP I-48
n PIN CONFIGURATIONS
A15 A14 A13 A12 A11 A10 A9 A8 NC NC WE CE2 NC UB LB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE1 A0
n BLOCK DIAGRAM
BH616UV8010TI
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3
Address Input Buffer
10 Row Decoder
1024
Memory Array
1024 x 8192
8192 DQ0 . . . . . . DQ15 . . . . . . 16 Data Input Buffer Data Output Buffer 16 512 Column Decoder 9 Address Input Buffer Control 16 Column I/O Write Driver Sense Amp
16
1 A B C D E F G H LB DQ8 DQ9 VSS VCC DQ14 DQ15 A18
2 OE UB DQ10 DQ11 DQ12 DQ13 NC A8
3 A0 A3 A5 A17 VSS A14 A12 A9
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CE1 DQ1 DQ3 DQ4 DQ5 WE A11
6 CE2 DQ0 DQ2 VCC VSS DQ6 DQ7 NC
CE2 CE1 WE OE UB LB VCC VSS
A18 A17 A15 A14 A13 A16 A2 A1 A0
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH616UV8010
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Revision 1.2 May. 2006
BH616UV8010
n PIN DESCRIPTIONS
Name
A0-A18 Address Input CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input
Function
These 19 address inputs select one of the 524,288 x 16 bit in the RAM
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. Lower byte and upper byte data input/output control pins.
WE Write Enable Input
OE Output Enable Input
LB and UB Data Byte Control Input DQ0-DQ15 Data Input/Output Ports VCC VSS
16 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
n TRUTH TABLE MODE
Chip De-selected (Power Down)
CE1
H X X L
CE2
X L X H H
WE
X X X H H
OE
X X X H H
LB
X X H L X L
UB
X X H X L L L H L L H
DQ0~DQ7 DQ8~DQ15 VCC CURRENT
High Z High Z High Z High Z High Z DOUT High Z DOUT DIN X DIN High Z High Z High Z High Z High Z DOUT DOUT High Z DIN DIN X ICCSB, ICCSB1 ICCSB, ICCSB1 ICCSB, ICCSB1 ICC ICC ICC ICC ICC ICC ICC ICC
Output Disabled L
Read
L
H
H
L
H L L
Write
L
H
L
X
H L
NOTES: H means VIH; L means VIL; X means don't care (Must be VIH or VIL state)
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Revision 1.2 May. 2006
BH616UV8010
n ABSOLUTE MAXIMUM RATINGS
SYMBOL
VTERM TBIAS TSTG PT IOUT
(1)
n OPERATING RANGE
UNITS
V
O
PARAMETER
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
RATING
-0.5(2) to 4.6V -40 to +125 -60 to +150 1.0 20
RANG
Industrial
AMBIENT TEMPERATURE
-40OC to + 85OC
VCC
1.65V ~ 3.6V
C C
O
n CAPACITANCE
(1)
(TA = 25 C, f = 1.0MHz)
O
W
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
mA CIN 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. -2.0V in case of AC pulse width less than 30 ns CIO Input Capacitance Input/Output Capacitance VIN = 0V VI/O = 0V 6 8 pF pF
1. This parameter is guaranteed and not 100% tested.
n DC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C)
PARAMETER NAME VCC VIL VIH IIL PARAMETER
Power Supply
VCC=1.8V VCC=3.6V
O
O
TEST CONDITIONS
MIN.
1.65 -0.3(2) 1.4 2.2 --
TYP.(1)
--
MAX.
3.6 0.4 0.6
UNITS
V
Input Low Voltage
--
V
Input High Voltage VIN = 0V to VCC, CE1 = VIH or CE2 = VIL VI/O = 0V to V CC,
VCC=1.8V VCC=3.6V
--
VCC+0.3(3)
V
Input Leakage Current
--
1
uA
ILO
Output Leakage Current
CE1 = VIH or CE2 = VIL or OE = VIH or UB = LB = VIH V CC = Max, IOL = 0.2mA V CC = Max, IOL = 2.0mA
VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V VCC=1.8V VCC=3.6V
--
--
1 0.2 0.4
uA
VOL VOH ICC ICC1 ICCSB ICCSB1
Output Low Voltage
-VCC-0.2 2.4 --
--
V
Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current - TTL
V CC = Min, IOH = -0.1mA V CC = Min, IOH = -1.0mA CE1 = VIL and CE2 = VIH, IDQ = 0mA, f = FMAX(4) CE1 = VIL and CE2 = VIH, IDQ = 0mA, f = 1MHz CE1 = VIH, or CE2 = VIL, IDQ = 0mA CE1VCC-0.2V or CE20.2V, VINV CC-0.2V or VIN0.2V
-6 8
-8 12 1.5 2.0 0.5 1.0
V
mA
--
1.0 1.5
mA
--
-2.0 2.5
(5)
mA
Standby Current - CMOS
--
12 15
uA
1. Typical characteristics are at TA=25OC and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. 4. FMAX=1/tRC. 5. VCC=3.0V R0201-BH616UV8010
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Revision 1.2 May. 2006
BH616UV8010
n DATA RETENTION CHARACTERISTICS (TA = -40 C to +85 C)
SYMBOL VDR ICCDR tCDR tR PARAMETER
VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time
O O
TEST CONDITIONS
CE1VCC-0.2V or CE20.2V, VINVCC-0.2V or VIN0.2V CE1VCC-0.2V or CE20.2V, VINVCC-0.2V or VIN0.2V
VCC=1.2V
MIN.
1.0 -0
TYP. (1)
-1.2 ---
MAX.
-7.0 ---
UNITS
V uA ns ns
See Retention Waveform tRC (2)
1. Typical characteristics are at TA=25OC and not 100% tested. 2. tRC = Read Cycle Time.
n LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
VCC
VIH
VCC
VDR1.0V
VCC
tCDR
CE1VCC - 0.2V
tR
VIH
CE1
n LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode VCC VDR1.0V
VCC
VCC
tCDR
tR
CE20.2V
CE2
VIL
VIL
n AC TEST CONDITIONS
(Test Load and Input/Output Reference)
n KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS MUST BE STEADY MAY CHANGE FROM "H" TO "L" MAY CHANGE FROM "L" TO "H" DON'T CARE ANY CHANGE PERMITTED DOES NOT APPLY OUTPUTS MUST BE STEADY WILL BE CHANGE FROM "H" TO "L" WILL BE CHANGE FROM "L" TO "H" CHANGE : STATE UNKNOW CENTER LINE IS HIGH INPEDANCE "OFF" STATE
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level tCLZ1, tCLZ2, tBE, tOLZ, tCHZ1, tCHZ2, tBDO, tOHZ, tWHZ, tOW Output Load Others
VCC / 0V 1V/ns 0.5Vcc CL = 5pF+1TTL CL = 30pF+1TTL ALL INPUT PULSES
1 TTL Output CL(1)
VCC GND
10%
90%
90% 10%
Rise Time: 1V/ns
Fall Time: 1V/ns
1. Including jig and scope capacitance.
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Revision 1.2 May. 2006
BH616UV8010
n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) READ CYCLE
JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 55ns DESCRIPTION Read Cycle Time Address Access Time Chip Select Access Time Chip Select Access Time Data Byte Control Access Time Output Enable to Output Valid Chip Select to Output Low Z Chip Select to Output Low Z Data Byte Control to Output Low Z Output Enable to Output Low Z Chip Select to Output High Z Chip Select to Output High Z (CE1) (CE2) (CE1) (CE2) (LB, UB) (CE1) (CE2) (LB, UB) MIN. 55 -----10 10 10 5 ----10 TYP. ---------------MAX. -55 55 55 55 30 ----25 25 25 25 -CYCLE TIME : 70ns MIN. 70 -----10 10 10 5 ----10 TYP. ---------------MAX. -70 70 70 70 35 ----30 30 30 30 -UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
O O
tAVAX tAVQX tE1LQV tE2LQV tBLQV tGLQV tE1LQX tE2LQX tBLQX tGLQX tE1HQZ tE2HQZ tBHQZ tGHQZ tAVQX
tRC tAA tACS1 tACS2 tBA tOE tCLZ1 tCLZ2 tBE tOLZ tCHZ1 tCHZ2 tBDO tOHZ tOH
Data Byte Control to Output High Z (LB, UB) Output Enable to Output High Z Data Hold from Address Change
n SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1
(1,2,4)
tRC ADDRESS tOH DOUT tAA tOH
R0201-BH616UV8010
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Revision 1.2 May. 2006
BH616UV8010
READ CYCLE 2
(1,3,4)
CE1 tACS1 CE2 tCLZ DOUT
(6)
tACS2
(5,6)
tCHZ
(5, 6)
READ CYCLE 3
(1, 4)
tRC ADDRESS tAA OE tOE CE1 tCLZ1 CE2 tCLZ2 LB, UB
(5) (5)
tOH
tOLZ tACS1 tOHZ tCHZ
(5)
(1,5)
tACS2
tCHZ2 tBA tBE tBDO
(2,5)
DOUT
NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL. 5. Transition is measured 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested.
R0201-BH616UV8010
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Revision 1.2 May. 2006
BH616UV8010
n AC ELECTRICAL CHARACTERISTICS (TA = -40 C to +85 C) WRITE CYCLE
JEDEC PARANETER PARAMETER NAME NAME DESCRIPTION Write Cycle Time Address Set up Time Address Valid to End of Write Chip Select to End of Write Data Byte Control to End of Write Write Pulse Width Write Recovery Time Write Recovery Time Write to Output High Z Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z End of Write to Output Active (CE1, WE) (CE2) (LB, UB) CYCLE TIME : 55ns MIN. 55 0 45 45 45 35 0 0 -25 0 -5 TYP. -------------MAX. --------20 --25 -CYCLE TIME : 70ns MIN. 70 0 60 60 60 35 0 0 -30 0 -5 TYP. -------------MAX. --------25 --30 -ns ns ns ns ns ns ns ns ns ns ns ns ns UNITS
O O
tAVAX tAVWL tAVWH tELWH tBLWH tWLWH tWHAX tE2LAX tWLQZ tDVWH tWHDX tGHQZ tWHQX
tWC tAS tAW tCW tBW tWP tWR1 tWR2 tWHZ tDW tDH tOHZ tOW
n SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1
(1)
tWC ADDRESS
OE tCW CE1
(5) (11)
tWR1
(3)
CE2
(5)
tCW LB, UB tAW WE tAS tOHZ DOUT
(4,10)
(11)
tBW
tWR2
(3)
tWP
(2)
tDH tDW DIN
R0201-BH616UV8010
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Revision 1.2 May. 2006
BH616UV8010
WRITE CYCLE 2 ADDRESS tCW
(11) (1,6)
tWC
CE1
(5)
CE2
(5)
tCW LB, UB
(12)
(11)
tBW tAW
tWR
(3)
WE tAS tWHZ DOUT
(4,10)
tWP
(2)
tOW tDW tDH
(8,9)
(7)
(8)
DIN
NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11. tCW is measured from the later of CE1 going low or CE2 going high to the end of write.
R0201-BH616UV8010
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Revision 1.2 May. 2006
BH616UV8010
n ORDERING INFORMATION
BH616UV8010
X
X
Z
YY
SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE I: -40oC ~ +85oC PACKAGE D: DICE A: BGA-48-0608 T: TSOP I-48
Note: Brilliance Semiconductor Inc. (BSI) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
1.2 Max.
BALL PITCH e = 0.75 D 8.0 E 6.0 N 48 D1 5.25 E1 3.75
D1
e
VIEW A
48 mini-BGA (6 x 8)
E1
R0201-BH616UV8010
9
Revision 1.2 May. 2006
BH616UV8010
n PACKAGE DIMENSIONS
TSOP I-48 Pin (12mm x 20mm)
R0201-BH616UV8010
10
Revision 1.2 May. 2006
BH616UV8010
n Revision History Revision No. 1.0 1.1 History Initial Production Version To improve access speed - from 70ns to 55ns Change I-grade operation temperature range - from -25OC to -40OC Draft Date July 15,2005 Dec. 23, 2005 Remark Initial
1.2
May. 25, 2006
R0201-BH616UV8010
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Revision 1.2 May. 2006

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